half subtractor and full subtractor
1) Half subtractor:
Circuit:
Truth table:
| A | B | DIFFERENCE | BORROW |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY HALF_SUB IS
PORT(A,B:IN STD_LOGIC ; DIFF,BORROW:OUT STD_LOGIC);
END HALF_SUB;
ARCHITECTURE ARCH_HALF_SUB OF HALF_SUB IS
BEGIN
DIFF <= A XOR B;
BORROW <= (NOT A) AND B;
END ARCH_HALF_SUB
Simulation waveform:
2) Full subtractor:
Circuit:
Truth table:
| A | B | C | DIFFERENCE | BORROW |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 1 | 1 |
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY FULL_SUB IS
PORT(A,B,C:IN STD_LOGIC ; DIFF,BORROW:OUT STD_LOGIC);
END FULL_SUB;
ARCHITECTURE ARCH_FULL_SUB OF FULL_SUB IS
BEGIN
DIFF <= A XOR B XOR C;
BORROW <= ((NOT A) AND B) OR ((NOT A) AND C) OR (B AND C);
END ARCH_FULL_SUB;
Simulation waveform:
