4×1 8×1 multiplexer 1×4 demux and 1×8 demux
4×1 Multiplexer
Code:
library ieee;
use ieee.std_logic_1164.all;
entity mux41 is
port ( d : in std_logic_vector (0 to 3);
s : in std_logic_vector (0 to 1);
o : out std_logic);
end mux41;
architecture vdc of mux41 is
begin
process (d,s)
begin
case s is
when “00” => o<= d(0);
when “01” => o<= d(1);
when “10” => o<= d(2);
when “11” => o<= d(3);
end case;
end process;
end vdc;
Simulation Waveform:
8×1 Multiplexer
Code:
library ieee;
use ieee.std_logic_1164.all;
entity mux81 is
port ( d : in std_logic_vector (0 to 7);
s : in std_logic_vector (0 to 2);
o : out std_logic);
end mux81;
architecture mux_archi of mux81 is
begin
process (d,s)
begin
case s is
when “000” => o<= d(0);
when “001” => o<= d(1);
when “010” => o<= d(2);
when “011” => o<= d(3);
when “100” => o<= d(4);
when “101” => o<= d(5);
when “110” => o<= d(6);
when “111” => o<= d(7);
when others => o<= ‘0’;
end case;
end process;
end mux_archi;
Simulation Waveform:
1×4 Demultiplexer
Code:
library ieee;
use ieee.std_logic_1164.all;
entity demux14 is
port ( i : in std_logic;
s : in std_logic_vector (0 to 1);
o : out std_logic_vector (0 to 3));
end demux14;
architecture demux_archi of demux14 is
begin
process (i,s)
begin
case s is
when "00" => o(0)<= i;
when "01" => o(1)<= i;
when "10" => o(2)<= i;
when "11" => o(3)<= i;
when others => o<= "0000";
end case;
end process;
end demux_archi;
Simulation Waveform:
1×8 Demultiplexer
Code:
library ieee;
use ieee.std_logic_1164.all;
entity demux18 is
port ( i : in std_logic;
s : in std_logic_vector (0 to 2);
o : out std_logic_vector (0 to 7));
end demux18;
architecture demux_archi of demux18 is
begin
process (i,s)
begin
o <= "00000000";
case s is
when "000" => o(0)<= i;
when "001" => o(1)<= i;
when "010" => o(2)<= i;
when "011" => o(3)<= i;
when "100" => o(4)<= i;
when "101" => o(5)<= i;
when "110" => o(6)<= i;
when "111" => o(7)<= i;
when others => o<= "00000000";
end case;
end process;
end demux_archi;
Simulation Waveform:
