Build and simulate 8×3 encoder and 3×8 decoder in VHDL

8×3 encoder and 3×8 decoder in VHDL

8×3 Encoder

Code: 

library ieee;
use ieee.std_logic_1164.all;

entity encoder_8x3 is
port (d : in std_logic_vector (7 downto 0);
      a,b,c : out std_logic);
end encoder_8x3;

architecture vdc of encoder_8x3 is 
begin
process (d)
begin
	a <= d(4) or d(5) or d(6) or d(7);
	b <= d(2) or d(3) or d(6) or d(7);
	c <= d(1) or d(3) or d(5) or d(7);
end process;
end vdc;

Simulation Result:

3×8 Decoder with active high enable

Code:

library ieee;
use ieee.std_logic_1164.all;
entity decoder_8x3 is
port (a,b,c,enable : in std_logic ;
		d : out std_logic_vector (0 to 7));
end decoder_8x3;
architecture vdc of decoder_8x3 is
begin
process (a,b,c)
begin
if enable = '1' then
	d(0) <= (not a) and (not b) and (not c);
	d(1) <= (not a) and (not b) and c;
	d(2) <= (not a) and (b) and (not c);
	d(3) <= (not a) and b and c;
	d(4) <= a and (not b) and (not c);
	d(5) <= a and (not b) and c;
	d(6) <= a and b and (not c);
	d(7) <= a and b and c;
else
d <= "11111111";
end if;
end process;
end vdc;

Simulation Result: