SR flip-flop and D flip-flop
D Flip – Flop with enable and reset
Code:
library ieee;
use ieee.std_logic_1164.all;
entity flip_flop is
port (clk,Din,rst,en : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
end flip_flop;
architecture my_flipflop of flip_flop is
signal t : std_logic;
begin
process (clk,en,Din,rst)
begin
if(en='0') then
Q <='Z';
Qnot <= 'Z';
elsif(rst='1') then
Q <='0';
Qnot <='1';
elsif(clk'event and clk='1') then
Q <= Din;
t <= Din;
Qnot <= not t;
end if;
end process;
end my_flipflop;
Simulation waveforms:
RS Flip-Flop
Code:
library ieee;
use ieee.std_logic_1164.all;
entity flip_flop is
port (clk,r,s : in std_logic;
Q: out std_logic;
Qnot : out std_logic);
end flip_flop;
architecture my_flipflop of flip_flop is
signal t1,t2 : std_logic;
begin
t1 <= r nor t2;
t2 <= s nor t1;
process (clk,r,s)
begin
if(clk'event and clk='1' ) then
if(r='0' and s='0') then
Q <=t1;
Qnot <= t2;
elsif(r='0' and s='1') then
Q <='1';
Qnot <='0';
elsif(r='1' and s='0') then
Q <='0';
Qnot <='1';
elsif(r='1' and s='1') then
Q <='X';
Qnot <='X';
end if;
end if;
end process;
end my_flipflop;
Simulation waveforms:
