vhdl

Build and simulate JK Flip-Flop and T-Flip-flop in VHDL

JK Flip-Flop and T Flip-Flop

JK Flip-Flop with active high reset input

JK Flip-Flop and T Flip-Flop
JK Flip-Flop and T Flip-Flop

Code:

entity flip_flop is 
  port (clk,J,K,rst : in std_logic;
        Q: out std_logic;
        Qnot : out std_logic);
 end flip_flop;
architecture my_flipflop of flip_flop is   
signal state: std_logic;
signal input: std_logic_vector(1 downto 0);
  begin
   input <= J & K;
    process(clk, rst) is
     begin
      if (rst='1') then
        state <= '0';
      elsif (clk'event and clk='1') then
       case (input) is
        when "11" => state <= not state;
        when "10" => state <= '1';
        when "01" => state <= '0';
        when "00" => state <= state;
        when others => null;
       end case;
      end if;
     end process;
    Q <= state;
    Qnot <= not state;	
end my_flipflop;

Simulation Waveforms:

JK Flip-Flop and T Flip-Flop

T Flip-Flop with enable and reset

Code:

library ieee;
use ieee.std_logic_1164.all;
entity flip_flop is 
  port (clk,t,en,rst : in std_logic;
        Q: out std_logic;
        Qnot : out std_logic);
 end flip_flop;
architecture my_flipflop of flip_flop is   
 signal op: std_logic;	
  begin		
   process(clk, rst) is
    begin
      if(en='0') then op<='Z';
      elsif (en='1' and rst='1') then
          op <= '0';
      elsif (clk'event and clk='1' and en='1') then
          if(t='1') then op <= not op;
          else op <= op;
          end if;
     end if;
  end process;
  Q <= op;
  Qnot <= not op;	
end my_flipflop; 

Simulation Waveforms:

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