simulate half adder and full adder
1) Half adder:
Circuit:
Truth table:
| A | B | SUM | CARRY |
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY HALF_ADDER IS
PORT(A,B:IN STD_LOGIC ; SUM,CARRY:OUT STD_LOGIC);
END HALF_ADDER;
ARCHITECTURE ARCH_HALF_ADDER OF HALF_ADDER IS
BEGIN
SUM <= A XOR B;
CARRY <= A AND B;
END ARCH_HALF_ADDER;
Simulation waveform:
2) Full adder:
Circuit:
Truth table:
| A | B | C | SUM | CARRY |
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Code:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL ;
ENTITY FULL_ADDER IS
PORT(A,B,C:IN STD_LOGIC ; SUM,CARRY:OUT STD_LOGIC);
END FULL_ADDER;
ARCHITECTURE ARCH_FULL_ADDER OF FULL_ADDER IS
BEGIN
SUM <= A XOR B XOR C;
CARRY <= (A AND B) OR (B AND C) OR (A AND C);
END ARCH_FULL_ADDER;
Simulation waveform:
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