simulate NAND and NOR gates as universal gates
- NAND gate as a universal gate:
FIGURE:
CODE:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NAND_UNI IS
PORT(A,B:IN STD_LOGIC;
AND_OUT,OR_OUT,NOT_OUT,XOR_OUT: OUT STD_LOGIC);
END NAND_UNI;
ARCHITECTURE BEHAVIORAL OF NAND_UNI IS
BEGIN
AND_OUT <= (A NAND B) NAND (A NAND B);
OR_OUT <= (A NAND A) NAND (B NAND B);
NOT_OUT <= (A NAND A);
XOR_OUT <= (A NAND (A NAND B)) NAND (B NAND (A NAND B));
END BEHAVIORAL;
WAVE FORMS:
- Nor gate as universal
FIGURE:
CODE:
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY NOR_UNI IS
PORT(A,B:IN STD_LOGIC;
AND_OUT,OR_OUT,NOT_OUT,XOR_OUT: OUT STD_LOGIC);
END NOR_UNI;
ARCHITECTURE BEHAVIORAL OF NOR_UNI IS
BEGIN
AND_OUT <= (A NOR B) NOR (A NOR B);
OR_OUT <= (A NOR A) NOR (B NOR B);
NOT_OUT <= (A NOR A);
XOR_OUT <= (A NOR (A NOR B)) NOR (B NOR (A NOR B));
END BEHAVIORAL;
WAVE FORMS:
