Build and simulate NAND, NOR, XOR and XNOR gates using basic gates in VHDL.

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LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY BASIC_GATE IS

PORT(A,B:IN STD_LOGIC;

                                NAND_OUT,NOR_OUT,XOR_OUT,XNOR_OUT: OUT STD_LOGIC);

END BASIC_GATE;

ARCHITECTURE BEHAVIORAL OF BASIC_GATE IS

BEGIN

                                NAND_OUT <= NOT (A AND B);

                                NOR_OUT <= NOT (A OR B);

                                XOR_OUT <= (A AND NOT(B)) OR (NOT(A) AND B);

                                XNOR_OUT <= (A AND B) OR (NOT(A) AND NOT(B));

END BEHAVIORAL;

 

 

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