Logic Gates verify and implement using VHDL code.

The logic gate is a circuit having one or more inputs and one output and output iis at logic level 0 or 1 for the definite conditions of input logic level.there are different types of logic gates such as AND , OR, NOT, NAND, NOR,EX-OR,EX-NOR etc.

Circuit:

Implement and verify Logic Gates Using VHDL code.
Implement and verify Logic Gates Using VHDL code.

Truth table:

INPUT:AINPUT:BORAND
0000
0110
1010
1111
INPUT:ANOT
01
10

CODE:

 

 

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY all_gate IS

PORT(A,B:IN STD_LOGIC;

                                OR_OUT,AND_OUT,EXOR_OUT,EXNOR_OUT,NOT_OUT: OUT STD_LOGIC);

END all_gate;

ARCHITECTURE all_gate OF all_gate IS

BEGIN

                                OR_OUT <= A OR B;

                                AND_OUT <= A AND B;

                                EXOR_OUT <= A XOR B;

                                EXNOR_OUT <= A XNOR B;

                                NOT_OUT <= NOT A;

END all_gate;

 

 

 

WAVE FORMS:

 

 

More info On wikipedia

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